//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 141732
// File Date           :  2012-12-05 16:55:57 +0000 (Wed, 05 Dec 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : HDL design file for AMBA interface block slave domain
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//                        nic400_ib_tpv_gp_apb4_ib_slave_domain_ysyx_rv32.v
//
//------------------------------------------------------------------------------
//
//  Overview
// ==========
//
//  Slave domain of AMBA Interface Block (IB) 'tpv_gp_apb4_ib'.
//
//  This IB is a component of AMIB named tpv_gp_apb4
//  
//
//           SIF prot axi4
//           MIF prot itb
//           SIF DW   32
//           MIF DW   32
//
//           MIF  itb_m
//           RIF  axi_r
//           IIF  iif
//           BIF  iif
//
//           Burstbreak  = false
//
//------------------------------------------------------------------------------

`include "nic400_ib_tpv_gp_apb4_ib_defs_ysyx_rv32.v"


module nic400_ib_tpv_gp_apb4_ib_slave_domain_ysyx_rv32
  (
  
    //axi4_s AXI bus

    //AW Channel
    awid_axi4_s,
    awaddr_axi4_s,
    awlen_axi4_s,
    awsize_axi4_s,
    awburst_axi4_s,
    awlock_axi4_s,
    awcache_axi4_s,
    awprot_axi4_s,
    awvalid_axi4_s,
    awregion_axi4_s,
    awready_axi4_s,

    //W Channel
    wdata_axi4_s,
    wstrb_axi4_s,
    wlast_axi4_s,
    wvalid_axi4_s,
    wready_axi4_s,

    //B Channel
    bid_axi4_s,
    bresp_axi4_s,
    bvalid_axi4_s,
    bready_axi4_s,

    //AR Channel
    arid_axi4_s,
    araddr_axi4_s,
    arlen_axi4_s,
    arsize_axi4_s,
    arburst_axi4_s,
    arlock_axi4_s,
    arcache_axi4_s,
    arprot_axi4_s,
    arvalid_axi4_s,
    arregion_axi4_s,
    arready_axi4_s,

    //R Channel
    rid_axi4_s,
    rdata_axi4_s,
    rresp_axi4_s,
    rlast_axi4_s,
    rvalid_axi4_s,
    rready_axi4_s,

    //Inter-domain IB bus

    //A Inter-domain bus
    a_data_async,
    a_rpntr_gry_async,
    a_rpntr_bin,
    a_wpntr_gry_async,

    //D Inter-domain bus
    d_data_async,
    d_rpntr_gry_async,
    d_rpntr_bin,
    d_wpntr_gry_async,

    //W Inter-domain bus
    w_data_async,
    w_rpntr_gry_async,
    w_rpntr_bin,
    w_wpntr_gry_async,

    //Clock and reset signals
    aclk_s,
    aresetn_s

  );



  // ---------------------------------------------------------------------------
  //  Port definitions
  // ---------------------------------------------------------------------------
  
  //axi4_s AXI bus


  //AW Channel
  input   [3:0]       awid_axi4_s;            //write id of axi4_s AXI bus AW channel
  input   [31:0]      awaddr_axi4_s;          //write address of axi4_s AXI bus AW channel
  input   [7:0]       awlen_axi4_s;           //write length field of axi4_s AXI bus AW channel
  input   [2:0]       awsize_axi4_s;          //write size of axi4_s AXI bus AW channel
  input   [1:0]       awburst_axi4_s;         //write burst length of axi4_s AXI bus AW channel
  input               awlock_axi4_s;          //write lock of axi4_s AXI bus AW channel
  input   [3:0]       awcache_axi4_s;         //write cache field of axi4_s AXI bus AW channel
  input   [2:0]       awprot_axi4_s;          //write prot field of axi4_s AXI bus AW channel
  input               awvalid_axi4_s;         //write valid of axi4_s AXI bus AW channel
  input   [3:0]       awregion_axi4_s;        //write region selection signal
  output              awready_axi4_s;         //write ready of axi4_s AXI bus AW channel

  //W Channel
  input   [31:0]      wdata_axi4_s;           //write data of axi4_s AXI bus W Channel
  input   [3:0]       wstrb_axi4_s;           //write strobes of axi4_s AXI bus W Channel
  input               wlast_axi4_s;           //write last of axi4_s AXI bus W Channel
  input               wvalid_axi4_s;          //write valid of axi4_s AXI bus W Channel
  output              wready_axi4_s;          //write ready of axi4_s AXI bus W Channel

  //B Channel
  output  [3:0]       bid_axi4_s;             //b response id of axi4_s AXI bus B Channel
  output  [1:0]       bresp_axi4_s;           //b response status of axi4_s AXI bus B Channel
  output              bvalid_axi4_s;          //b response valid of axi4_s AXI bus B Channel
  input               bready_axi4_s;          //b response ready of axi4_s AXI bus B Channel

  //AR Channel
  input   [3:0]       arid_axi4_s;            //read id of axi4_s AXI bus AR Channel
  input   [31:0]      araddr_axi4_s;          //read address of axi4_s AXI bus AR Channel
  input   [7:0]       arlen_axi4_s;           //read length of axi4_s AXI bus AR Channel
  input   [2:0]       arsize_axi4_s;          //read size of axi4_s AXI bus AR Channel
  input   [1:0]       arburst_axi4_s;         //read burst length of axi4_s AXI bus AR Channel
  input               arlock_axi4_s;          //read lock of axi4_s AXI bus AR Channel
  input   [3:0]       arcache_axi4_s;         //read cache field of axi4_s AXI bus AR Channel
  input   [2:0]       arprot_axi4_s;          //read prot field of axi4_s AXI bus AR Channel
  input               arvalid_axi4_s;         //read valid of axi4_s AXI bus AR Channel
  input   [3:0]       arregion_axi4_s;        //read region selection signal
  output              arready_axi4_s;         //read ready of axi4_s AXI bus AR Channel

  //R Channel
  output  [3:0]       rid_axi4_s;             //read id of axi4_s AXI bus R Channel
  output  [31:0]      rdata_axi4_s;           //read data of axi4_s AXI bus R Channel
  output  [1:0]       rresp_axi4_s;           //read response status of axi4_s AXI bus R Channel
  output              rlast_axi4_s;           //read last of axi4_s AXI bus R Channel
  output              rvalid_axi4_s;          //read valid of axi4_s AXI bus R Channel
  input               rready_axi4_s;          //read ready of axi4_s AXI bus R Channel

  //Inter-domain IB bus


  //A Inter-domain bus
  output  [61:0]      a_data_async;           //A Channel Data
  input   [1:0]       a_rpntr_gry_async;      //A Channel Read Pointer (GRY)
  input               a_rpntr_bin;            //A Channel Read Pointer (BIN) for data mux
  output  [1:0]       a_wpntr_gry_async;      //A Channel Read Pointer (GRY)

  //D Inter-domain bus
  input   [39:0]      d_data_async;           //D Channel Data
  output  [1:0]       d_rpntr_gry_async;      //D Channel Read Pointer (GRY)
  output              d_rpntr_bin;            //D Channel Read Pointer (BIN) for data mux
  input   [1:0]       d_wpntr_gry_async;      //D Channel Read Pointer (GRY)

  //W Inter-domain bus
  output  [36:0]      w_data_async;           //W Channel Data
  input   [1:0]       w_rpntr_gry_async;      //W Channel Read Pointer (GRY)
  input               w_rpntr_bin;            //W Channel Read Pointer (BIN) for data mux
  output  [1:0]       w_wpntr_gry_async;      //W Channel Read Pointer (GRY)

  //Clock and reset signals
  input               aclk_s;                 //main clock
  input               aresetn_s;              //main reset
   

  // ---------------------------------------------------------------------------
  // Internal signals
  // ---------------------------------------------------------------------------

  // A Channel wires at boundary
  
  wire                a_boundary_src_valid;
  wire                a_boundary_src_ready;

  wire [61:0]         a_boundary_src_data;     // concatenation of the inputs
  wire [61:0]         a_boundary_dst_data;     // concatenation of the registered inputs


  // D Channel wires at boundary
  
  wire                d_boundary_dst_valid;
  wire                d_boundary_dst_ready;

  wire [39:0]         d_boundary_dst_data;     // concatenation of the registered inputs


  // W Channel wires at boundary
  
  wire                w_boundary_src_valid;
  wire                w_boundary_src_ready;

  wire [36:0]         w_boundary_src_data;     // concatenation of the inputs
  wire [36:0]         w_boundary_dst_data;     // concatenation of the registered inputs


  // AW Channel wires at slave_port
  
  wire [60:0]         aw_slave_port_src_data;     // concatenation of the inputs
  wire [60:0]         aw_slave_port_dst_data;     // concatenation of the registered inputs

  wire                aw_slave_port_dst_valid;
  wire                aw_slave_port_dst_ready;
  wire                aw_slave_port_src_valid;
  wire                aw_slave_port_src_ready;

  // AR Channel wires at slave_port
  
  wire [60:0]         ar_slave_port_src_data;     // concatenation of the inputs
  wire [60:0]         ar_slave_port_dst_data;     // concatenation of the registered inputs

  wire                ar_slave_port_dst_valid;
  wire                ar_slave_port_dst_ready;
  wire                ar_slave_port_src_valid;
  wire                ar_slave_port_src_ready;

  wire [38:0]         r_slave_port_src_data;     // concatenation of the inputs
  wire [38:0]         r_slave_port_dst_data;     // concatenation of the registered inputs

  wire [36:0]         w_slave_port_src_data;     // concatenation of the inputs
  wire [36:0]         w_slave_port_dst_data;     // concatenation of the registered inputs

  wire [5:0]          b_slave_port_src_data;     // concatenation of the inputs
  wire [5:0]          b_slave_port_dst_data;     // concatenation of the registered inputs

  wire [1:0]          a_rpntr_gry_async;             // gray encoded rd-pointer for A channel
  wire                a_rpntr_bin;             // binary encoded pointer for read data mux
  wire [1:0]          a_wpntr_gry_async;             // gray encoded wr-pointer for full/empty calc
  
  wire [1:0]          w_rpntr_gry_async;             // gray encoded rd-pointer for W channel
  wire                w_rpntr_bin;             // binary encoded pointer for read data mux
  wire [1:0]          w_wpntr_gry_async;             // gray encoded wr-pointer for full/empty calc
  
  wire [1:0]          d_rpntr_gry_async;             // gray encoded rd-pointer for D channel
  wire                d_rpntr_bin;             // binary encoded pointer for read data mux
  wire [1:0]          d_wpntr_gry_async;             // gray encoded wr-pointer for full/empty calc

  // ITB_iif IIF

  // A Channel
  wire                awrite_iif;
  wire                avalid_iif;
  wire [31:0]         aaddr_iif;
  wire [7:0]          alen_iif;
  wire [2:0]          asize_iif;
  wire [1:0]          aburst_iif;
  wire           alock_iif;
  wire [3:0]          acache_iif;
  wire [2:0]          aprot_iif;
  wire [3:0]          aid_iif;
  wire                aready_iif;
  wire [3:0]          aregion_iif;

  // D Channel
  wire                dbnr_iif;
  wire                dvalid_iif;
  wire                dlast_iif;
  wire [31:0]         ddata_iif;
  wire [1:0]          dresp_iif;
  wire [3:0]          did_iif;
  wire                dready_iif;

  // AXI_axi_r RIF

  // AR Channel
  wire                arvalid_axi_r;
  wire [31:0]         araddr_axi_r;
  wire [7:0]          arlen_axi_r;
  wire [2:0]          arsize_axi_r;
  wire [1:0]          arburst_axi_r;
  wire           arlock_axi_r;
  wire [3:0]          arcache_axi_r;
  wire [2:0]          arprot_axi_r;
  wire [3:0]          arregion_axi_r;
  wire [3:0]          arid_axi_r;
  wire                arready_axi_r;

  // AW Channel
  wire                awvalid_axi_r;
  wire [31:0]         awaddr_axi_r;
  wire [7:0]          awlen_axi_r;
  wire [2:0]          awsize_axi_r;
  wire [1:0]          awburst_axi_r;
  wire           awlock_axi_r;
  wire [3:0]          awcache_axi_r;
  wire [2:0]          awprot_axi_r;
  wire [3:0]          awregion_axi_r;
  wire [3:0]          awid_axi_r;
  wire                awready_axi_r;


  // R Channel
  wire                rvalid_axi_r;
  wire                rlast_axi_r;
  wire [31:0]         rdata_axi_r;
  wire [1:0]          rresp_axi_r;
  wire [3:0]          rid_axi_r;
  wire                rready_axi_r;

  // W Channel
  wire                wvalid_axi_r;
  wire                wlast_axi_r;
  wire [31:0]         wdata_axi_r;
  wire [3:0]          wstrb_axi_r;
  wire                wready_axi_r;

  // B Channel
  wire                bvalid_axi_r;
  wire [1:0]          bresp_axi_r;
  wire [3:0]          bid_axi_r;
  wire                bready_axi_r;

  // ---------------------------------------------------------------------------

  // ---------------------------------------------------------------------------
  //  start of code
  // ---------------------------------------------------------------------------





  //----------------------------------------------------------------------------
  // AXI to ITB
  //----------------------------------------------------------------------------
  nic400_ib_tpv_gp_apb4_ib_axi_to_itb_ysyx_rv32 u_axi_to_itb
  (
    .awid           (awid_axi_r),
    .awaddr         (awaddr_axi_r),
    .awlen          (awlen_axi_r),
    .awsize         (awsize_axi_r),
    .awburst        (awburst_axi_r),
    .awlock         (awlock_axi_r),
    .awcache        (awcache_axi_r),
    .awprot         (awprot_axi_r),
    .awregion       (awregion_axi_r),
    .awvalid        (awvalid_axi_r),
    .awready        (awready_axi_r),

    
    .bid            (bid_axi_r),
    .bresp          (bresp_axi_r),
    .bvalid         (bvalid_axi_r),
    .bready         (bready_axi_r),
    
    .arid           (arid_axi_r),
    .araddr         (araddr_axi_r),
    .arlen          (arlen_axi_r),
    .arsize         (arsize_axi_r),
    .arburst        (arburst_axi_r),
    .arlock         (arlock_axi_r),
    .arcache        (arcache_axi_r),
    .arprot         (arprot_axi_r),
    .arregion       (arregion_axi_r),
    .arvalid        (arvalid_axi_r),
    .arready        (arready_axi_r),
    
    .rid            (rid_axi_r),
    .rdata          (rdata_axi_r),
    .rresp          (rresp_axi_r),
    .rlast          (rlast_axi_r),
    .rvalid         (rvalid_axi_r),
    .rready         (rready_axi_r),

    .awrite         (awrite_iif),
    .aid            (aid_iif),
    .aaddr          (aaddr_iif),
    .alen           (alen_iif),
    .asize          (asize_iif),
    .aburst         (aburst_iif),
    .alock          (alock_iif),
    .acache         (acache_iif),
    .aprot          (aprot_iif),
    .aregion        (aregion_iif),
    .avalid         (avalid_iif),
    .aready         (aready_iif),

    .dbnr           (dbnr_iif),
    .did            (did_iif),
    .ddata          (ddata_iif),
    .dresp          (dresp_iif),
    .dlast          (dlast_iif),
    .dvalid         (dvalid_iif),
    .dready         (dready_iif),

    .aclk           (aclk_s),
    .aresetn        (aresetn_s)
  );



  // ---------------------------------------------------------------------------


  // ---------------------------------------------------------------------------
  // A Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign a_boundary_src_data = {
          aid_iif,
          awrite_iif,
          aaddr_iif,
          alen_iif,
          asize_iif,
          aburst_iif,
          alock_iif,
          acache_iif,
          aregion_iif,
          aprot_iif};


  assign a_boundary_src_valid = avalid_iif;
  assign aready_iif = a_boundary_src_ready;

  assign a_data_async = a_boundary_dst_data;
  
  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign w_boundary_src_data = {
          wdata_axi_r,
          wstrb_axi_r,
          wlast_axi_r};


  assign w_boundary_src_valid = wvalid_axi_r;
  assign wready_axi_r = w_boundary_src_ready;

  assign w_data_async = w_boundary_dst_data;
  

  // ---------------------------------------------------------------------------
  // D Channel timing block wiring at boundary
  // ---------------------------------------------------------------------------

  // expand the concatenated registered values to the master port outputs
  assign {
          did_iif,
          dbnr_iif,
          ddata_iif,
          dresp_iif,
          dlast_iif} = d_boundary_dst_data;

  assign d_boundary_dst_ready = dready_iif;
  assign dvalid_iif = d_boundary_dst_valid;




  // ---------------------------------------------------------------------------
  // AW Channel timing block wiring at slave_port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign aw_slave_port_src_data = {
          awid_axi4_s,
          awaddr_axi4_s[31:0],
          awlen_axi4_s,
          awsize_axi4_s,
          awburst_axi4_s,
          awlock_axi4_s,
          awcache_axi4_s,
          awregion_axi4_s,
          awprot_axi4_s};

  // expand the concatenated registered values to the master port outputs
  assign {
          awid_axi_r,
          awaddr_axi_r[31:0],
          awlen_axi_r,
          awsize_axi_r,
          awburst_axi_r,
          awlock_axi_r,
          awcache_axi_r,
          awregion_axi_r,
          awprot_axi_r} = aw_slave_port_dst_data;


  assign awvalid_axi_r = aw_slave_port_dst_valid;
  assign aw_slave_port_dst_ready = awready_axi_r;

  assign aw_slave_port_src_valid = awvalid_axi4_s;
  assign awready_axi4_s = aw_slave_port_src_ready;


  // ---------------------------------------------------------------------------
  // AR Channel timing block wiring at slave_port
  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign ar_slave_port_src_data = {
          arid_axi4_s,
          araddr_axi4_s[31:0],
          arlen_axi4_s,
          arsize_axi4_s,
          arburst_axi4_s,
          arlock_axi4_s,
          arcache_axi4_s,
          arregion_axi4_s,
          arprot_axi4_s};

  // expand the concatenated registered values to the master port outputs
  assign {
          arid_axi_r,
          araddr_axi_r[31:0],
          arlen_axi_r,
          arsize_axi_r,
          arburst_axi_r,
          arlock_axi_r,
          arcache_axi_r,
          arregion_axi_r,
          arprot_axi_r} = ar_slave_port_dst_data;


  assign arvalid_axi_r = ar_slave_port_dst_valid;
  assign ar_slave_port_dst_ready = arready_axi_r;

  assign ar_slave_port_src_valid = arvalid_axi4_s;
  assign arready_axi4_s = ar_slave_port_src_ready;


  // ---------------------------------------------------------------------------
  // R Channel timing block wiring at slave_port
  // No register specified for R Channel: Wire striaght across

  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign r_slave_port_src_data = {
          rid_axi_r,
          rdata_axi_r,
          rresp_axi_r,
          rlast_axi_r};

  // expand the concatenated registered values to the master port outputs
  assign {
          rid_axi4_s,
          rdata_axi4_s,
          rresp_axi4_s,
          rlast_axi4_s} = r_slave_port_dst_data;


  assign r_slave_port_dst_data = r_slave_port_src_data;

  assign rvalid_axi4_s = rvalid_axi_r;
  assign rready_axi_r = rready_axi4_s;


  // ---------------------------------------------------------------------------
  // W Channel timing block wiring at slave_port
  // No register specified for W Channel: Wire striaght across

  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign w_slave_port_src_data = {
          wdata_axi4_s,
          wstrb_axi4_s,
          wlast_axi4_s};

  // expand the concatenated registered values to the master port outputs
  assign {
          wdata_axi_r,
          wstrb_axi_r,
          wlast_axi_r} = w_slave_port_dst_data;


  assign w_slave_port_dst_data = w_slave_port_src_data;

  assign wvalid_axi_r = wvalid_axi4_s;
  assign wready_axi4_s = wready_axi_r;


  // ---------------------------------------------------------------------------
  // B Channel timing block wiring at slave_port
  // No register specified for B Channel: Wire striaght across

  // ---------------------------------------------------------------------------

  // the inputs are concatenated to interface to the generic register set
  assign b_slave_port_src_data = {
          bid_axi_r,
          bresp_axi_r};

  // expand the concatenated registered values to the master port outputs
  assign {
          bid_axi4_s,
          bresp_axi4_s} = b_slave_port_dst_data;


  assign b_slave_port_dst_data = b_slave_port_src_data;

  assign bvalid_axi4_s = bvalid_axi_r;
  assign bready_axi_r = bready_axi4_s;

  // ---------------------------------------------------------------------------
  // Instantiation of Timing Isolation Blocks
  // ---------------------------------------------------------------------------
  //  A Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 62
  nic400_ib_tpv_gp_apb4_ib_a_fifo_wr_ysyx_rv32
  u_a_fifo_wr
    (
     // global interconnect inputs
     .wresetn               (aresetn_s),
     .wclk                  (aclk_s),
     // inputs
     .src_valid             (a_boundary_src_valid),
     .src_data              (a_boundary_src_data),
     .rpntr_gry_async       (a_rpntr_gry_async),
     .rpntr_bin             (a_rpntr_bin),

     // outputs
     .src_ready             (a_boundary_src_ready),
     .dst_data              (a_boundary_dst_data),
     .wpntr_gry_async       (a_wpntr_gry_async)
     );



  //  D Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 40
  nic400_ib_tpv_gp_apb4_ib_d_fifo_rd_ysyx_rv32
  u_d_fifo_rd
    (
     // global interconnect inputs
     .rresetn               (aresetn_s),
     .rclk                  (aclk_s),
     // inputs
     .src_data              (d_data_async),
     .dst_ready             (d_boundary_dst_ready),
     .wpntr_gry_async       (d_wpntr_gry_async),

     // outputs
     .dst_data              (d_boundary_dst_data),
     .dst_valid             (d_boundary_dst_valid),
     .rpntr_gry_async       (d_rpntr_gry_async),
     .rpntr_bin             (d_rpntr_bin)
     );



  //  W Channel Timing Isolation Register Block on boundary

  // HNDSHK_MODE = fifo
  // PAYLOAD_WIDTH = 37
  nic400_ib_tpv_gp_apb4_ib_w_fifo_wr_ysyx_rv32
  u_w_fifo_wr
    (
     // global interconnect inputs
     .wresetn               (aresetn_s),
     .wclk                  (aclk_s),
     // inputs
     .src_valid             (w_boundary_src_valid),
     .src_data              (w_boundary_src_data),
     .rpntr_gry_async       (w_rpntr_gry_async),
     .rpntr_bin             (w_rpntr_bin),

     // outputs
     .src_ready             (w_boundary_src_ready),
     .dst_data              (w_boundary_dst_data),
     .wpntr_gry_async       (w_wpntr_gry_async)
     );



  //  AW Channel Timing Isolation Register Block on slave_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 61
  nic400_ib_tpv_gp_apb4_ib_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       61  // Payload Width
     )
  u_aw_slave_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn_s),
     .aclk                  (aclk_s),
     // inputs
     .src_valid             (aw_slave_port_src_valid),
     .src_data              (aw_slave_port_src_data),
     .dst_ready             (aw_slave_port_dst_ready),

     // outputs
     .src_ready             (aw_slave_port_src_ready),
     .dst_data              (aw_slave_port_dst_data),
     .dst_valid             (aw_slave_port_dst_valid)
     );



  //  AR Channel Timing Isolation Register Block on slave_port

  // HNDSHK_MODE = rev
  // PAYLOAD_WIDTH = 61
  nic400_ib_tpv_gp_apb4_ib_chan_slice_ysyx_rv32
    #(
       `RS_REV_REG,  // Handshake Mode
       61  // Payload Width
     )
  u_ar_slave_port_chan_slice
    (
     // global interconnect inputs
     .aresetn               (aresetn_s),
     .aclk                  (aclk_s),
     // inputs
     .src_valid             (ar_slave_port_src_valid),
     .src_data              (ar_slave_port_src_data),
     .dst_ready             (ar_slave_port_dst_ready),

     // outputs
     .src_ready             (ar_slave_port_src_ready),
     .dst_data              (ar_slave_port_dst_data),
     .dst_valid             (ar_slave_port_dst_valid)
     );



  // W channel is set to wires at slave_port.
    

  // ---------------------------------------------------------------------------

endmodule

`include "nic400_ib_tpv_gp_apb4_ib_undefs_ysyx_rv32.v"




// --================================= End ===================================--
